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...the world's most energy friendly microcontrollers
7 MSC - Memory System Controller
Quick Facts
What?
The user can perform Flash memory read,
read configuration and write operations
through the Memory System Controller
(MSC) .
Why?
0 1 2 3
4
01000101011011100110010101110010
01100111011110010010000001001101
01101001011000110111001001101111
00100000011100100111010101101100
01100101011100110010000001110100
01101000011001010010000001110111
01101111011100100110110001100100
00100000011011110110011000100000
01101100011011110111011100101101
01100101011011100110010101110010
01100111011110010010000001101101
01101001011000110111001001101111
01100011011011110110111001110100
01110010011011110110110001101100
01100101011100100010000001100100
01100101011100110110100101100111
01101110001000010100010101101110
The MSC allows the application code, user
data and flash lock bits to be stored in non-
volatile Flash memory. Certain memory
system functions, such as program memory
wait-states and bus faults are also configured
from the MSC peripheral register interface,
giving the developer the ability to dynamically
customize the memory system performance,
security level, energy consumption and error
handling capabilities to the requirements at
hand.
How?
The MSC integrates a low-energy Flash
IP with a charge pump, enabling minimum
energy consumption while eliminating the
need for external programming voltage to
erase the memory. An easy to use write and
erase interface is supported by an internal,
fixed-frequency oscillator and autonomous
flash timing and control reduces software
complexity while not using other timer
resources.
Application code may dynamically scale
between high energy optimization and
high code execution performance through
advanced read modes.
7.1 Introduction
The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The
flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided
into two blocks; the main block and the information block. Program code is normally written to the main
block. Additionally, the information block is available for special user data and flash lock bits. There is
also a read-only page in the information block containing system and device calibration data. Read and
write operations are supported in the energy modes EM0 and EM1.
7.2 Features
? AHB read interface
? Scalable access performance to optimize the Cortex-M3 code interface
? Zero wait-state access up to 16 MHz and one wait-state for 16 MHz and above
? Advanced energy optimization functionality
2011-04-12 - d0001_Rev1.10
27
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